Conventionally, for an integrated circuit, such as a memory, that did not provide a data valid signal, a worst case timing is used to determine frequency of operation between the integrated circuit and another integrated circuit. However, heretofore, this worst case timing analysis was difficult to arrive at due to a complex interaction, for example variation in timing parameters, such as deterministic jitter, random jitter, and duty cycle distortion, or minimum versus maximum timings for input/output drivers.
Heretofore, in practice, a user would have to do a rough approximation of a worst case timing analysis, and then hone such an approximation by testing an actual interface between two integrated circuits. This could prove costly, both in terms of engineering time and laboratory resources, as well as design impact, as a substantially inaccurate approximation may result in over consumption of clock resources or a redesign.
Accordingly, it would be desirable and useful to provide a worst case timing analysis that avoids one or more of the above-mentioned limitations.